235 search results - page 31 / 47 » On the Inertia of the Asynchronous Circuits |
115
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TCAD
2002
15 years 1 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
100
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DATE
2002
IEEE
15 years 6 months ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
102
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ASYNC
2003
IEEE
15 years 7 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
105
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ASYNC
2007
IEEE
15 years 8 months ago
2007
IEEE
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
108
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TCAD
2008
15 years 1 months ago
2008
State encoding is one of the most difficult problems in the synthesis of asynchronous controllers. This paper presents a method that can solve the problem of large controllers spec...