This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
This paper presents an analysis and comparison between synchronous and delay-insensitive asynchronous logic circuits on thermal distributions for investigating novel solutions to t...
Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran...
Abstract. Balanced asynchronous circuits have been touted as a superior replacement for conventional synchronous circuits. To assess these claims, we have designed, manufactured an...
Jacques J. A. Fournier, Simon W. Moore, Huiyun Li,...