373 search results - page 27 / 75 » On the Iterated Hairpin Completion |
FPGA
1998
ACM
15 years 4 months ago
1998
ACM
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in...
105
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TCS
2011
14 years 6 months ago
2011
We propose a formal definition of Wolfram’s notion of computational process based on iterated transducers together with a weak observer, a model of computation that captures so...
106
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SECON
2007
IEEE
15 years 6 months ago
2007
IEEE
—Wireless Sensor Networks (WSNs) require robustness against channel induced errors while retransmission based schemes prove too costly for energy constrained sensor nodes. Channe...
113
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IWMM
2010
Springer
15 years 4 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...