548 search results - page 35 / 110 » On the Limitations of Power Macromodeling Techniques |
JSA
2008
14 years 11 months ago
2008
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
171
Voted
BWCCA
2010
14 years 6 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
118
Voted
HPCA
2012
IEEE
13 years 6 months ago
2012
IEEE
Modern memory systems rely on spatial locality to provide high bandwidth while minimizing memory device power and cost. The trend of increasing the number of cores that share memo...
VLSID
2000
IEEE
15 years 3 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
ICCAD
2010
IEEE
14 years 9 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...