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» On the Limitations of Power Macromodeling Techniques
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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 6 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
88
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ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
15 years 8 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
HIPC
2007
Springer
15 years 5 months ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif
ICFEM
2004
Springer
15 years 4 months ago
Guiding Spin Simulation
Abstract. In this paper we present a technique for the Spin tool, inspired by practical experiences with Spin and a FireWire protocol. We show how to guide simulations with Spin, b...
Nicolae Goga, Judi Romijn
AI
2010
Springer
14 years 11 months ago
Property persistence in the situation calculus
We develop a new automated reasoning technique for the situation calculus that can handle a class of queries containing universal quantication over situation terms. Although such ...
Ryan F. Kelly, Adrian R. Pearce