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» On the Meaning of Logical Completeness
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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 2 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DSN
2000
IEEE
15 years 2 months ago
An Automatic SPIN Validation of a Safety Critical Railway Control System
This paper describes an experiment in formal specification and validation performed in the context of an industrial joint project. The project involved an Italian company working...
Stefania Gnesi, Diego Latella, Gabriele Lenzini, C...
MSE
1999
IEEE
118views Hardware» more  MSE 1999»
15 years 2 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
MM
1998
ACM
79views Multimedia» more  MM 1998»
15 years 2 months ago
Organizing Multicast Receivers Deterministically by Packet-Loss Correlation
The ability to trace multicast paths is currently available in the Internet by means of IGMP MTRACE packets. We introduce Tracer, the rst protocol that organizes the receivers of ...
Brian Neil Levine, Sanjoy Paul, J. J. Garcia-Luna-...
HPCN
1998
Springer
15 years 2 months ago
A Barotropic Global Ocean Model and its Parallel Implementation on Unstructured Grids
Unstructured grids can represent the complex geometry of the ocean basin with high delity. The lack of development tools supporting irregular grid problems discourages the use of ...
Hakan Öksüzoglu, A. G. M. van Hees