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IPPS
2010
IEEE
14 years 10 months ago
On the parallelisation of MCMC-based image processing
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
IPPS
2010
IEEE
14 years 10 months ago
Speculative execution on multi-GPU systems
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
Gregory F. Diamos, Sudhakar Yalamanchili
103
Voted
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
14 years 4 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
101
Voted
CEC
2009
IEEE
15 years 7 months ago
Task decomposition and evolvability in intrinsic evolvable hardware
— Many researchers have encountered the problem that the evolution of electronic circuits becomes exponentially more difficult when problems with an increasing number of outputs...
Tüze Kuyucu, Martin Trefzer, Julian Francis M...
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
15 years 6 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...