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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 7 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
119
Voted
CF
2010
ACM
15 years 7 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
GSN
2009
Springer
189views Sensor Networks» more  GSN 2009»
15 years 6 months ago
Deploying a Wireless Sensor Network in Iceland
A wireless sensor network deployment on a glacier in Iceland is described. The system uses power management as well as power harvesting to provide long-term environment sensing. Ad...
Kirk Martinez, Jane K. Hart, Royan Ong
133
Voted
CASES
2007
ACM
15 years 5 months ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula
113
Voted
CCS
2006
ACM
15 years 5 months ago
Safety analysis of usage control authorization models
The usage control (UCON) model was introduced as a unified approach to capture a number of extensions for traditional access control models. While the policy specification flexibi...
Xinwen Zhang, Ravi S. Sandhu, Francesco Parisi-Pre...