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» On the Role of Evolvability for Architectural Design
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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
14 years 9 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
CASES
2008
ACM
14 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ISLPED
2010
ACM
231views Hardware» more  ISLPED 2010»
14 years 10 months ago
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero bo...
Yibo Chen, Jishen Zhao, Yuan Xie
MIDDLEWARE
2007
Springer
15 years 4 months ago
A Utility-Aware Middleware Architecture for Decentralized Group Communication Applications
Abstract. The success of Internet telephony services like Skype illustrates the feasibility of utilizing unstructured Peer-to-Peer (P2P) networks as an economical platform for supp...
Jianjun Zhang, Ling Liu, Lakshmish Ramaswamy, Gong...
87
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ICC
2007
IEEE
170views Communications» more  ICC 2007»
15 years 4 months ago
Evaluating Techniques for Network Layer Independence in Cognitive Networks
— Cognitive networks are the latest progression of cognitive functionality into the networking stack, an effort which began with a layer one and two focus on cognitive radios, an...
Muthukumaran Pitchaimani, Benjamin J. Ewy, Joseph ...