90 search results - page 10 / 18 » On the Structure of Industrial SAT Instances |
69
Voted
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
84
Voted
TCAD
2002
14 years 9 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
AAAI
2010
14 years 11 months ago
2010
Planning as satisfiability is a principal approach to planning with many eminent advantages. The existing planning as satisfiability techniques usually use encodings compiled from...
100
Voted
DAC
2005
ACM
14 years 11 months ago
2005
ACM
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...