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» On the Use of Formal Techniques for Validation
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FMICS
2009
Springer
15 years 6 months ago
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
Matthias Raffelsieper, Mohammad Reza Mousavi, Jan-...
DAC
2006
ACM
16 years 19 days ago
Formal analysis of hardware requirements
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
Ingo Pill, Simone Semprini, Roberto Cavada, Marco ...
ISIM
2007
15 years 1 months ago
Formal Computation Independent Model of the Problem Domain within the MDA
The proposed approach called Topological Functioning Modeling for Model Driven Architecture (TFMfMDA) uses formal mathematical foundations of Topological Functioning Model. It intr...
Janis Osis, Erika Asnina, Andrejs Grave
UML
1998
Springer
15 years 3 months ago
The UML as a Formal Modeling Notation
The Uni ed Modeling Language UML is rapidly emerging as a de-facto standard for modelling OO systems. Given this role, it is imperative that the UML needs a well-de ned, fully expl...
Andy Evans, Robert B. France, Kevin Lano, Bernhard...
ISSTA
2012
ACM
13 years 2 months ago
ViewPoints: differential string analysis for discovering client- and server-side input validation inconsistencies
Since web applications are easily accessible, and often store a large amount of sensitive user information, they are a common target for attackers. In particular, attacks that foc...
Muath Alkhalaf, Shauvik Roy Choudhary, Mattia Fazz...