Sciweavers

3742 search results - page 14 / 749
» On the Use of Formal Techniques for Validation
Sort
View
SEW
2006
IEEE
15 years 5 months ago
Retrenching the Purse: Finite Exception Logs, and Validating the Small
The Mondex Electronic Purse is an outstanding example of industrial scale formal refinement, and was the first verification to achieve ITSEC level E6 certification. A formal a...
Richard Banach, Michael Poppleton, Susan Stepney
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
15 years 5 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
DAC
2009
ACM
16 years 21 days ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
USAB
2007
15 years 26 days ago
Improving Interactive Systems Usability Using Formal Description Techniques: Application to HealthCare
In this paper we argue that the formal analysis of an interactive medical system can improve their usability evaluation such that potential erroneous interactions are identified an...
Philippe A. Palanque, Sandra Basnyat, David Navarr...
RTSS
1999
IEEE
15 years 4 months ago
On the Use of Formal Techniques for Analyzing Dependable Real-Time Protocols
The e ective design of composite dependable and real-time protocols entails demonstrating their proof of correctness and, in practice, the e cient delivery of services. We focus o...
Purnendu Sinha, Neeraj Suri