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» On the Use of Formal Techniques for Validation
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UML
2004
Springer
15 years 5 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
FLAIRS
1998
15 years 1 months ago
Investigating the Validity of a Test Case Selection Methodology for Expert System Validation
Providing assurances of performance is an important aspect of successful development and commercialization of expert systems. However, this can only be done if the quality of the ...
Jan-Eike Michels, Thomas Abel, Rainer Knauf, Aveli...
FM
1999
Springer
114views Formal Methods» more  FM 1999»
15 years 4 months ago
Integrating Formal Description Techniques
Abstract. Using graphical description techniques for formal system development has become a common approach in many tools. Often multiple description techniques are used to represe...
Bernhard Schätz, Franz Huber
MCS
2010
Springer
15 years 6 months ago
Estimation of the Number of Clusters Using Multiple Clustering Validity Indices
One of the challenges in unsupervised machine learning is finding the number of clusters in a dataset. Clustering Validity Indices (CVI) are popular tools used to address this pro...
Krzysztof Kryszczuk, Paul Hurley
FIW
1998
104views Communications» more  FIW 1998»
15 years 1 months ago
Validating Architectural Feature Descriptions using LOTOS
The phases of the ANISE project (Architectural Notions In Service Engineering) are briefly explained with reference to the work reported here. An outline strategy is given for tra...
Kenneth J. Turner