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» On the Use of Formal Techniques for Validation
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ENTCS
2006
131views more  ENTCS 2006»
14 years 11 months ago
The Case for Analog Circuit Verification
The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases...
Chris J. Myers, Reid R. Harrison, David Walter, Ni...
CII
2006
67views more  CII 2006»
14 years 11 months ago
A formal verification framework and associated tools for Enterprise Modeling: Application to UEML
The aim of this paper is to propose and apply a verification and validation approach to Enterprise Modeling that enables the user to improve the relevance and correctness, the sui...
Vincent Chapurlat, Bernard Kamsu Foguem, Fran&cced...
FATES
2003
Springer
15 years 5 months ago
Using a Software Testing Technique to Improve Theorem Proving
Most efforts to combine formal methods and software testing go in the direction of exploiting formal methods to solve testing problems, most commonly test case generation. Here we ...
Reiner Hähnle, Angela Wallenburg
PADS
2009
ACM
15 years 6 months ago
An Approach for Validation of Semantic Composability in Simulation Models
Semantic composability aims to ensure that the composition of simulation components is meaningful in terms of their expressed behavior, and achieves the desired objective of the n...
Claudia Szabo, Yong Meng Teo
FM
1997
Springer
258views Formal Methods» more  FM 1997»
15 years 3 months ago
Consistent Graphical Specification of Distributed Systems
: The widely accepted possible benefits of formal methods on the one hand and their minor use compared to informal or graphical description techniques on the other hand have repeat...
Franz Huber, Bernhard Schätz, Geralf Einert