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» On the Use of Formal Techniques for Validation
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IJCSA
2006
95views more  IJCSA 2006»
14 years 11 months ago
Modeling and Formal Verification of DHCP Using SPIN
The Dynamic Host Configuration Protocol (DHCP) is a widely used communication protocol. In this paper, a portion of the protocol is chosen for modeling and verification, namely th...
Syed M. S. Islam, Mohammed H. Sqalli, Sohel Khan
HASE
2008
IEEE
14 years 12 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
80
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SEKE
2004
Springer
15 years 5 months ago
Predicting UML Statechart Diagrams Understandability Using Fuzzy Logic-Based Techniques
In this work, we present an application of the Fuzzy Logic in the field of prediction in Software Engineering. We specifically use the Fuzzy Prototypical Knowledge Discovery for ch...
José A. Cruz-Lemus, Marcela Genero, Jos&eac...
PASTE
2004
ACM
15 years 5 months ago
Validation of assembler programs for DSPs: a static analyzer
Digital Signal Processors are widely used in critical embedded systems to pilot low-level, often critical functionalities. We describe a static analyzer based on abstract interpre...
Matthieu Martel
AOSE
2004
Springer
15 years 5 months ago
A Formal Approach to Design and Reuse Agent and Multiagent Models
While there are many useful models of agents and multi-agent systems, they are typically defined in an informal way and applied in an ad-hoc fashion. Consequently, multi-agent sys...
Vincent Hilaire, Olivier Simonin, Abder Koukam, Ja...