3742 search results - page 37 / 749 » On the Use of Formal Techniques for Validation |
129
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MTV
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...
101
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SAS
2009
Springer
2009
Springer
Abstract Parsing: Static Analysis of Dynamically Generated String Output Using LR-Parsing Technology
16 years 9 days ago
parsing: static analysis of dynamically generated string output using LR-parsing technology Kyung-Goo Doh1 , Hyunha Kim1 , David A. Schmidt2 1 Hanyang University, Ansan, South Kore...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
METRICS
2003
IEEE
15 years 5 months ago
2003
IEEE
As distributed technologies become more widely used, the need for assessing the quality of distributed applications correspondingly increases. Despite the rich body of research an...
106
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ICONS
2009
IEEE
15 years 6 months ago
2009
IEEE
Most recent software related accidents have been system accidents. To validate the absence of system hazards concerning dysfunctional interactions, industrials call for approaches...