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» On the Use of Formal Techniques for Validation
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WSC
2001
15 years 1 months ago
Implementation of response surface methodology using variance reduction techniques in semiconductor manufacturing
Semiconductor manufacturing is generally considered a cyclic industry. As such, individual producers able to react quickly and appropriately to market conditions will have a compe...
Charles D. McAllister, Bertan Altuntas, Matthew Fr...
JCP
2008
116views more  JCP 2008»
14 years 11 months ago
Formal Verification and Visualization of Security Policies
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
Luay A. Wahsheh, Daniel Conte de Leon, Jim Alves-F...
CAISE
2003
Springer
15 years 5 months ago
Evaluation of the SRA Tool Using Data Mining Techniques
This paper describes a validation approach of a socio-technical design support system using data mining techniques. Bayesian Belief Networks (BBN) are used to assess human error an...
Andreas Gregoriades, Alistair G. Sutcliffe, Harala...
COLT
1998
Springer
15 years 4 months ago
Cross-Validation for Binary Classification by Real-Valued Functions: Theoretical Analysis
This paper concerns the use of real-valued functions for binary classification problems. Previous work in this area has concentrated on using as an error estimate the `resubstitut...
Martin Anthony, Sean B. Holden
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
15 years 5 months ago
An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling
This paper describes a random jitter measurement technique using simple algorithms and comparator sampling. The approach facilitates using Automated Test Equipment (ATE) to valida...
Dongwoo Hong, Cameron Dryden, Gordon Saksena