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» On the Values of Reducibility Candidates
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ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
14 years 7 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
HPCA
2001
IEEE
15 years 10 months ago
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
Bart Goeman, Hans Vandierendonck, Koenraad De Boss...
ICCD
2000
IEEE
75views Hardware» more  ICCD 2000»
15 years 6 months ago
Hybridizing and Coalescing Load Value Predictors
Most well-performing load value predictors are hybrids that combine multiple predictors into one. Such hybrids are often large. To reduce their size and to improve their performan...
Martin Burtscher, Benjamin G. Zorn
ICRA
2009
IEEE
227views Robotics» more  ICRA 2009»
15 years 4 months ago
Adaptive autonomous control using online value iteration with gaussian processes
— In this paper, we present a novel approach to controlling a robotic system online from scratch based on the reinforcement learning principle. In contrast to other approaches, o...
Axel Rottmann, Wolfram Burgard
ISMVL
2007
IEEE
95views Hardware» more  ISMVL 2007»
15 years 4 months ago
Simulation of Gate Circuits with Feedback in Multi-Valued Algebras
Simulation of gate circuits is an efficient method of detecting hazards and oscillations that may occur because of delays. Ternary simulation consists of two algorithms, A and B,...
Janusz A. Brzozowski, Yuli Ye