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» On the Verification of Temporal Properties
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134
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FDL
2007
IEEE
15 years 7 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
104
Voted
ICWE
2007
Springer
15 years 7 months ago
Tool Support for Model Checking of Web Application Designs
: In this work we report our experience in applying model checking techniques to the analysis of static and dynamic properties of Web application models. We propose a mix of tools ...
Marco Brambilla, Jordi Cabot, Nathalie Moreno
90
Voted
ISPW
2005
IEEE
15 years 6 months ago
Process Programming to Support Medical Safety: A Case Study on Blood Transfusion
Medical errors are now recognized as a major cause of untimely deaths or other adverse medical outcomes. To reduce the number of medical errors, the Medical Safety Project at the U...
Lori A. Clarke, Yao Chen, George S. Avrunin, Bin C...
102
Voted
ICSE
2004
IEEE-ACM
15 years 6 months ago
Precise Modeling of Design Patterns in UML
Prior research attempts to formalize the structure of object-oriented design patterns for a more precise specification of design patterns. It also allows automation support to be ...
Jeffrey Ka-Hing Mak, Clifford Sze-Tsan Choy, Danie...
80
Voted
EUROMICRO
2000
IEEE
15 years 5 months ago
Formal Coverification of Embedded Systems Using Model Checking
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...