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DAC
2004
ACM
16 years 6 hour ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
DAC
2005
ACM
16 years 6 hour ago
Race-condition-aware clock skew scheduling
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
DAC
2006
ACM
16 years 6 hour ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
DAC
2006
ACM
16 years 6 hour ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...
SIGSOFT
2001
ACM
15 years 11 months ago
Combining UML and formal notations for modelling real-time systems
This article explores a dual approach to real-time software development. Models are written in UML, as this is expected to be relatively easy and economic. Then models are automat...
Luigi Lavazza, Gabriele Quaroni, Matteo Venturelli