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» On the complexity of stratified logics
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ESOP
2010
Springer
15 years 8 months ago
Precise and Automated Contract-based Reasoning for Verification and Certification of Information Flow Properties of Programs wit
Abstract. Embedded information assurance applications that are critical to national and international infrastructures, must often adhere to certification regimes that require infor...
Torben Amtoft, John Hatcliff and Edwin Rodríguez
ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
15 years 8 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
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ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
15 years 8 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
15 years 8 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
15 years 7 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang