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» On the complexity of stratified logics
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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
15 years 7 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
85
Voted
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
15 years 5 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...
TOOLS
2009
IEEE
15 years 5 months ago
Reusing and Composing Tests with Traits
Single inheritance often forces developers to duplicate code and logic. This widely recognized situation affects both business code and tests. In a large and complex application w...
Stéphane Ducasse, Damien Pollet, Alexandre ...
IWMM
2009
Springer
164views Hardware» more  IWMM 2009»
15 years 5 months ago
Live heap space analysis for languages with garbage collection
The peak heap consumption of a program is the maximum size of the live data on the heap during the execution of the program, i.e., the minimum amount of heap space needed to run t...
Elvira Albert, Samir Genaim, Miguel Gómez-Z...
IEEESCC
2007
IEEE
15 years 4 months ago
Swift: Fast, Reliable, Loosely Coupled Parallel Computation
A common pattern in scientific computing involves the execution of many tasks that are coupled only in the sense that the output of one may be passed as input to one or more other...
Yong Zhao, Mihael Hategan, Ben Clifford, Ian T. Fo...