Sciweavers

7197 search results - page 106 / 1440
» On the computational power of BlenX
Sort
View
DAC
2007
ACM
15 years 11 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih...
DAC
1998
ACM
15 years 11 months ago
Policy Optimization for Dynamic Power Management
Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states,...
Giuseppe A. Paleologo, Luca Benini, Alessandro Bog...
DAC
2002
ACM
15 years 11 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
15 years 10 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
15 years 10 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan