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DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 2 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
ICC
2000
IEEE
143views Communications» more  ICC 2000»
15 years 2 months ago
An Analytical Approach for Closed-Loop Power Control Error Estimations in CDMA Cellular Systems
—This paper proposes an analytical study which aims at evaluating the received power statistics in DS-CDMA cellular systems which use a closed-loop power control scheme to compen...
Andrea Abrardo, Giuliano Benelli, Giovanni Giamben...
DAC
2000
ACM
15 years 11 months ago
Power analysis of embedded operating systems
The increasing complexity and software content of embedded systems has led to the common use of sophisticated system software that helps applications use the underlying hardware r...
Robert P. Dick, Ganesh Lakshminarayana, Anand Ragh...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
15 years 10 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
VLSID
2001
IEEE
132views VLSI» more  VLSID 2001»
15 years 10 months ago
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL component...
Nachiketh R. Potlapally, Michael S. Hsiao, Anand R...