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VLSID
2008
IEEE
153views VLSI» more  VLSID 2008»
15 years 10 months ago
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
Yuanlin Lu, Vishwani D. Agrawal
VLSID
2006
IEEE
140views VLSI» more  VLSID 2006»
15 years 10 months ago
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
VLSID
2006
IEEE
85views VLSI» more  VLSID 2006»
15 years 10 months ago
A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters
This paper presents a novel architecture using the decorrelating (DECOR) transformation technique when applied to an LMS adaptive filter. The DECOR transform has been evaluated pr...
Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan,...
VLSID
2004
IEEE
126views VLSI» more  VLSID 2004»
15 years 10 months ago
Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes
In order to break the 100 W average power barrier of a wireless microsensor node, aggressive design methodologies need to be developed. Dynamic voltage scaling should be more aggr...
David D. Wentzloff, Benton H. Calhoun, Rex Min, Al...
ISCAS
2006
IEEE
100views Hardware» more  ISCAS 2006»
15 years 4 months ago
Power system on a chip (PSoC)
— This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a Power System on a Chip (PSoC). The paper wil...
Chika O. Nwankpa, A. S. Deese, Qingyan Liu, Aaron ...