Sciweavers

7197 search results - page 175 / 1440
» On the computational power of BlenX
Sort
View
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
15 years 10 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
94
Voted
HIPEAC
2009
Springer
15 years 5 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
89
Voted
SIGCOMM
2009
ACM
15 years 4 months ago
Game action based power management for multiplayer online game
Current mobile devices embrace a wide range of functionalities including high speed network support, hardware accelerated 3D graphics, and multimedia capabilities. These capabilit...
Bhojan Anand, Akkihebbal L. Ananda, Mun Choon Chan...
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
15 years 10 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
70
Voted
VLSID
2004
IEEE
146views VLSI» more  VLSID 2004»
15 years 10 months ago
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...