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DAC
2002
ACM
15 years 11 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
75
Voted
DAC
2005
ACM
15 years 11 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
MOBIHOC
2005
ACM
15 years 9 months ago
Temporal properties of low power wireless links: modeling and implications on multi-hop routing
Recently, several studies have analyzed the statistical properties of low power wireless links in real environments, clearly demonstrating the differences between experimentally o...
Alberto Cerpa, Jennifer L. Wong, Miodrag Potkonjak...
ALGOSENSORS
2009
Springer
15 years 4 months ago
A Note on Uniform Power Connectivity in the SINR Model
In this paper we study the connectivity problem for wireless networks under the Signal to Interference plus Noise Ratio (SINR) model. Given a set of radio transmitters distributed ...
Chen Avin, Zvi Lotker, Francesco Pasquale, Yvonne ...
MICRO
2008
IEEE
136views Hardware» more  MICRO 2008»
15 years 4 months ago
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott ...