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APCSAC
2006
IEEE
15 years 4 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
DATE
2005
IEEE
162views Hardware» more  DATE 2005»
15 years 3 months ago
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
UML 2.0 provides a rich set of diagrams for systems documentation and specification. Many efforts have been undertaken to employ different aspects of UML for multiple domains, mai...
Tim Schattkowsky, Wolfgang Müller 0003, Achim...
FPT
2005
IEEE
170views Hardware» more  FPT 2005»
15 years 3 months ago
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences
This paper describes a class of FPGA-specific uniform random number generators with a 2k −1 length period, which can provide k random bits per-cycle for the cost of k Lookup Ta...
David B. Thomas, Wayne Luk
INTETAIN
2005
Springer
15 years 3 months ago
Grounding Emotions in Human-Machine Conversational Systems
In this paper we investigate the role of user emotions in human-machine goal-oriented conversations. There has been a growing interest in predicting emotions from acted and non-act...
Giuseppe Riccardi, Dilek Z. Hakkani-Tür
ICNP
2003
IEEE
15 years 3 months ago
Delay Analysis of IEEE 802.11 in Single-Hop Networks
This paper presents an analytical model to compute the average service time and jitter experienced by a packet when transmitted in a saturated IEEE 802.11 ad hoc network. In contr...
Marcelo M. Carvalho, J. J. Garcia-Luna-Aceves