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» On the energy-efficiency of speculative hardware
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106
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MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
15 years 6 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
94
Voted
VLSISP
2008
118views more  VLSISP 2008»
15 years 11 days ago
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
Abstract. The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and u...
Awais M. Kamboh, Andrew Mason, Karim G. Oweiss
ICPP
2000
IEEE
15 years 4 months ago
Partial Resolution in Data Value Predictors
Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism (ILP). An outcome of an instructio...
Toshinori Sato, Itsujiro Arita
98
Voted
ICCD
2003
IEEE
104views Hardware» more  ICCD 2003»
15 years 9 months ago
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
Jaume Abella, Antonio González
88
Voted
FPL
2009
Springer
105views Hardware» more  FPL 2009»
15 years 5 months ago
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming
As a step torward a viable, single-issue out-of-order soft core, this work presents Copy-Free Checkpointing (CFC), an FPGA-friendly register renaming design. CFC supports speculat...
Kaveh Aasaraai, Andreas Moshovos