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RTSS
2006
IEEE
15 years 6 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
SIGMETRICS
2005
ACM
117views Hardware» more  SIGMETRICS 2005»
15 years 6 months ago
Classifying scheduling policies with respect to higher moments of conditional response time
In addition to providing small mean response times, modern applications seek to provide users predictable service and, in some cases, Quality of Service (QoS) guarantees. In order...
Adam Wierman, Mor Harchol-Balter
SCHULE
2001
Springer
15 years 5 months ago
Co-operative ICT-supported learning. A practical approach to design
Abstract: Education is changing, following changes in society. The focus is shifting from teaching towards learning. And Informatics, more particularly Information and Communicatio...
Tom J. van Weert
CASES
2005
ACM
15 years 2 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
FGCS
2008
105views more  FGCS 2008»
15 years 25 days ago
The Grid Workloads Archive
While large grids are currently supporting the work of thousands of scientists, very little is known about their actual use. Due to strict organizational permissions, there are fe...
Alexandru Iosup, Hui Li, Mathieu Jan, Shanny Anoep...