903 search results - page 29 / 181 » On the reduction of a random basis |
ISVLSI
2008
IEEE
15 years 8 months ago
2008
IEEE
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
120
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DFT
2003
IEEE
15 years 7 months ago
2003
IEEE
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
TCAD
2008
15 years 1 months ago
2008
Abstract--In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures...
115
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NIPS
2007
15 years 3 months ago
2007
To accelerate the training of kernel machines, we propose to map the input data to a randomized low-dimensional feature space and then apply existing fast linear methods. The feat...
127
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NIPS
2007
15 years 3 months ago
2007
We propose a novel method for linear dimensionality reduction of manifold modeled data. First, we show that with a small number M of random projections of sample points in RN belo...