111 search results - page 8 / 23 » On the value locality of store instructions |
HPCA
2007
IEEE
16 years 3 days ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
HPCA
2008
IEEE
16 years 3 days ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
FOSSACS
2010
Springer
15 years 6 months ago
2010
Springer
Every algebraic theory gives rise to a monad, and monads allow a meta-language which is a basic programming language with sideeffects. Equations in the algebraic theory give rise ...
MICRO
1997
IEEE
15 years 4 months ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...