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ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
15 years 4 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
110
Voted
ARC
2008
Springer
115views Hardware» more  ARC 2008»
15 years 3 months ago
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applica...
Antonio Roldao Lopes, George A. Constantinides
ARCS
2008
Springer
15 years 3 months ago
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...
Joachim Keinert, Christian Haubelt, Jürgen Te...
114
Voted
GRAPHICSINTERFACE
2000
15 years 2 months ago
High-Quality Interactive Lumigraph Rendering Through Warping
We introduce an algorithm for high-quality, interactive light field rendering from only a small number of input images with dense depth information. The algorithm bridges the gap ...
Hartmut Schirmacher, Wolfgang Heidrich, Hans-Peter...
UAI
2000
15 years 2 months ago
The Anchors Hierarchy: Using the Triangle Inequality to Survive High Dimensional Data
This paper is about the use of metric data structures in high-dimensionalor non-Euclidean space to permit cached sufficientstatisticsaccelerationsof learning algorithms. It has re...
Andrew W. Moore