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FPL
2008
Springer
116views Hardware» more  FPL 2008»
15 years 1 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
WMPI
2004
ACM
15 years 5 months ago
Evaluating kilo-instruction multiprocessors
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. ...
Marco Galluzzi, Ramón Beivide, Valentin Pue...
IPPS
2008
IEEE
15 years 6 months ago
High-speed string searching against large dictionaries on the Cell/B.E. Processor
Our digital universe is growing, creating exploding amounts of data which need to be searched, protected and filtered. String searching is at the core of the tools we use to curb...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...
IPPS
1999
IEEE
15 years 4 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
15 years 5 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...