Sciweavers

191 search results - page 24 / 39
» On-Chip Communication Architecture for OC-768 Network Proces...
Sort
View
132
Voted
AINA
2004
IEEE
15 years 5 months ago
Parallel PageRank Computation on a Gigabit PC Cluster
Efficient computing the PageRank scores for a large web graph is actually one of the hot issues in Web-IR community. Recent researches propose to accelerate the computation, both ...
Bundit Manaskasemsak, Arnon Rungsawang
CISIS
2009
IEEE
15 years 8 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
119
Voted
NOCS
2009
IEEE
15 years 8 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
109
Voted
ICCD
2000
IEEE
107views Hardware» more  ICCD 2000»
15 years 10 months ago
Architectural Impact of Secure Socket Layer on Internet Servers
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
Krishna Kant, Ravishankar K. Iyer, Prasant Mohapat...
SIGCOMM
2009
ACM
15 years 8 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy