11 search results - page 1 / 3 » On-Chip Jitter Measurement for Phase Locked Loops |
99
Voted
ITC
1997
IEEE
15 years 6 months ago
1997
IEEE
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
DFT
2002
IEEE
15 years 6 months ago
2002
IEEE
123
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
100
click to vote
DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...
94
Voted
ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
- This paper presents a simulation tool targeted specifically at bang-bang type phase locked loop systems. The aim of this simulator is to quickly and accurately predict important ...