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» On-Chip Stochastic Communication
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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 3 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ASAP
2006
IEEE
131views Hardware» more  ASAP 2006»
15 years 1 months ago
A Generic Multi-Phase On-Chip Traffic Generation Environment
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three importan...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
ICCD
2002
IEEE
109views Hardware» more  ICCD 2002»
15 years 6 months ago
Physical Planning Of On-Chip Interconnect Architectures
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand fo...
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
80
Voted
NOCS
2007
IEEE
15 years 3 months ago
Implementing DSP Algorithms with On-Chip Networks
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...
Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
91
Voted
IESS
2007
Springer
165views Hardware» more  IESS 2007»
15 years 3 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt