496 search results - page 6 / 100 » On-Chip Stochastic Communication |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
ICCAD
2000
IEEE
15 years 1 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
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Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
ICPADS
2008
IEEE
15 years 3 months ago
2008
IEEE
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC [16]. The Quarc scheme significantly outperforms the Spidergon NoC through balancing t...