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» On-chip logic minimization
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DAC
2006
ACM
15 years 10 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
WWW
2007
ACM
15 years 10 months ago
Just the right amount: extracting modules from ontologies
The ability to extract meaningful fragments from an ontology is key for ontology re-use. We propose a definition of a module that guarantees to completely capture the meaning of a...
Bernardo Cuenca Grau, Ian Horrocks, Yevgeny Kazako...
POPL
2009
ACM
15 years 10 months ago
Relaxed memory models: an operational approach
Memory models define an interface between programs written in some language and their implementation, determining which behaviour the memory (and thus a program) is allowed to hav...
Gérard Boudol, Gustavo Petri
CHI
2004
ACM
15 years 10 months ago
Single-handed interaction techniques for multiple pressure-sensitive strips
We present a set of interaction techniques that make novel use of a small pressure-sensitive pad to allow one-handed direct control of a large number of parameters. The surface of...
Gábor Blaskó, Steven Feiner
CADE
2006
Springer
15 years 10 months ago
Inferring Network Invariants Automatically
Abstract. Verification by network invariants is a heuristic to solve uniform verification of parameterized systems. Given a system P, a network invariant for P is that abstracts th...
Olga Grinchtein, Martin Leucker, Nir Piterman