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» On-chip logic minimization
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VTS
2003
IEEE
115views Hardware» more  VTS 2003»
15 years 3 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
SIGIR
2003
ACM
15 years 3 months ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder
ADBIS
2003
Springer
194views Database» more  ADBIS 2003»
15 years 3 months ago
Rule-Based Generation of XML DTDs from UML Class Diagrams
We present an approach of how to extract automatically an XML document structure from a conceptual data model that describes the content of a document. We use UML class diagrams as...
Thomas Kudrass, Tobias Krumbein
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
15 years 2 months ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
VR
2002
IEEE
210views Virtual Reality» more  VR 2002»
15 years 2 months ago
Distributed Applications for Collaborative Augmented Reality
This paper focuses on the distributed architecture of the collaborative augmented reality system Studierstube. The system allows multiple users to experience a shared 3D workspace...
Dieter Schmalstieg, Gerd Hesina