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» On-chip logic minimization
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FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
15 years 2 months ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
MICRO
2000
IEEE
133views Hardware» more  MICRO 2000»
15 years 2 months ago
Compiler controlled value prediction using branch predictor based confidence
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
Eric Larson, Todd M. Austin
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
15 years 2 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley
ICCD
1999
IEEE
136views Hardware» more  ICCD 1999»
15 years 2 months ago
ActiveOS: Virtualizing Intelligent Memory
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
COLT
1999
Springer
15 years 2 months ago
On a Generalized Notion of Mistake Bounds
This paper proposes the use of constructive ordinals as mistake bounds in the on-line learning model. This approach elegantly generalizes the applicability of the on-line mistake ...
Sanjay Jain, Arun Sharma