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» On-chip logic minimization
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ACSC
2004
IEEE
15 years 1 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
DAC
2004
ACM
15 years 1 months ago
Implicit pseudo boolean enumeration algorithms for input vector control
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
Kaviraj Chopra, Sarma B. K. Vrudhula
CP
2006
Springer
15 years 1 months ago
Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
Michele Lombardi, Michela Milano
FPL
2004
Springer
119views Hardware» more  FPL 2004»
15 years 1 months ago
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
Sandeep S. Kumar, Christof Paar
FPL
2006
Springer
113views Hardware» more  FPL 2006»
15 years 1 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...