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» On-chip logic minimization
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FSTTCS
2006
Springer
15 years 1 months ago
Monitoring of Real-Time Properties
This paper presents a construction for runtime monitors that check real-time properties expressed in timed LTL (TLTL). Due to D'Souza's results, TLTL can be considered a ...
Andreas Bauer 0002, Martin Leucker, Christian Scha...
ICALP
2000
Springer
15 years 1 months ago
Generating Partial and Multiple Transversals of a Hypergraph
We consider two natural generalizations of the notion of transversal to a finite hypergraph, arising in data-mining and machine learning, the so called multiple and partial transve...
Endre Boros, Vladimir Gurvich, Leonid Khachiyan, K...
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 1 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
ICCAD
1995
IEEE
97views Hardware» more  ICCAD 1995»
15 years 1 months ago
Interface co-synthesis techniques for embedded systems
A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that ...
Pai H. Chou, Ross B. Ortega, Gaetano Borriello
AINA
2010
IEEE
15 years 1 months ago
PRoPHET+: An Adaptive PRoPHET-Based Routing Protocol for Opportunistic Network
Abstract—We propose PRoPHET+, a routing scheme for opportunistic networks designed to maximize successful data delivery rate and minimize transmission delay. PRoPHET+ computes a ...
Ting-Kai Huang, Chia-Keng Lee, Ling-Jyh Chen