704 search results - page 11 / 141 » On-chip logic minimization |
ASYNC
2001
IEEE
15 years 1 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
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FPGA
1992
ACM
15 years 1 months ago
1992
ACM
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
AAAI
2000
14 years 11 months ago
2000
The task of generating minimal models of a knowledge base is a significant computational problem in artificial intelligence. This task is at the computational heart of diagnosis s...
CODES
2003
IEEE
15 years 3 months ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...