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» On-chip logic minimization
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LOGCOM
2007
72views more  LOGCOM 2007»
14 years 9 months ago
Classical Modal Display Logic in the Calculus of Structures and Minimal Cut-free Deep Inference Calculi for S5
We begin by showing how to faithfully encode the Classical Modal Display Logic (CMDL) of Wansing into the Calculus of Structures (CoS) of Guglielmi. Since every CMDL calculus enjo...
Rajeev Goré, Alwen Tiu
DLT
2009
14 years 7 months ago
Branching-Time Temporal Logics with Minimal Model Quantifiers
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
Fabio Mogavero, Aniello Murano
STOC
2006
ACM
170views Algorithms» more  STOC 2006»
15 years 10 months ago
Hardness of approximate two-level logic minimization and PAC learning with membership queries
Producing a small DNF expression consistent with given data is a classical problem in computer science that occurs in a number of forms and has numerous applications. We consider ...
Vitaly Feldman
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
15 years 4 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
LICS
2005
IEEE
15 years 3 months ago
Model Checking Vs. Generalized Model Checking: Semantic Minimizations for Temporal Logics
Three-valued models, in which properties of a system are either true, false or unknown, have recently been advocated as a better representation for reactive program abstractions g...
Patrice Godefroid, Michael Huth