704 search results - page 15 / 141 » On-chip logic minimization |
179
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WEA
2010
Springer
15 years 4 months ago
2010
Springer
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
GLVLSI
2003
IEEE
15 years 3 months ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
CSREAESA
2004
14 years 11 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
IAT
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—In semantic matchmaking processes it is often useful, when the obtained match is not full, to provide explanations for the mismatch, to leverage further interaction and/...
103
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AISC
2004
Springer
15 years 3 months ago
2004
Springer
ion Within Partial Deduction for Linear Logic . . . . . . . . . . . . . . . . . 52 P. K¨ungas A Decision Procedure for Equality Logic with Uninterpreted Functions . . . 66 O. Tver...