704 search results - page 16 / 141 » On-chip logic minimization |
CDES
2006
14 years 11 months ago
2006
- Most of the direct-cover Boolean minimization techniques use a four step cyclic algorithm. First, the algorithm chooses an On-minterm; second, it generates the set of prime impli...
105
click to vote
DDECS
2009
IEEE
15 years 4 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
ISMVL
2009
IEEE
15 years 4 months ago
2009
IEEE