704 search results - page 24 / 141 » On-chip logic minimization |
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
EUSFLAT
2009
14 years 7 months ago
2009
Abstract-- A portfolio model to minimize the risk of falling under uncertainty is discussed. The risk of falling is represented by the value-at-risk of rate of return. Introducing ...
INFOCOM
2012
IEEE
13 years 7 days ago
2012
IEEE
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
INTEGRATION
2008
14 years 9 months ago
2008
In this paper an efficient algorithm for the synthesis and exact minimization of ESCT(Exclusive or Sum of Complex Terms) expressions for Boolean functions of at most six variables...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...