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» On-chip logic minimization
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ASPDAC
2005
ACM
87views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Static power minimization in current-mode circuits
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
M. S. Bhat, H. S. Jamadagni
CDES
2008
87views Hardware» more  CDES 2008»
14 years 11 months ago
Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7
In this paper an algorithm is proposed for the synthesis and exact minimization of ESCT (Exclusive or Sum of Complex Terms) expressions for Boolean functions of up to seven comple...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...
AAAI
2008
15 years 4 days ago
Hyperequivalence of Logic Programs with Respect to Supported Models
Recent research in nonmonotonic logic programming has focused on program equivalence relevant for program optimization and modular programming. So far, most results concern the st...
Miroslaw Truszczynski, Stefan Woltran
ISLPED
2006
ACM
70views Hardware» more  ISLPED 2006»
15 years 3 months ago
Sub-threshold design: the challenges of minimizing circuit energy
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
Benton H. Calhoun, Alice Wang, Naveen Verma, Anant...
ICNC
2005
Springer
15 years 3 months ago
On the Categorizing of Simply Separable Relations in Partial Four-Valued Logic
In completeness theories of multiple-valued logic, the characterization of Sheffer functions is an important problem,and the solution can be reduced to determining the minimal co...
Renren Liu, Zhiwei Gong, Fen Xu