704 search results - page 29 / 141 » On-chip logic minimization |
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
FM
2008
Springer
14 years 11 months ago
2008
Springer
Declarative specifications exhibit a variety of problems, such as inadvertently overconstrained axioms and underconstrained conjectures, that are hard to diagnose with model checki...
ICCAD
1999
IEEE
15 years 2 months ago
1999
IEEE
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
ITC
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
IJCAI
2003
14 years 11 months ago
2003
Inconsistencies frequently occur in knowledge about the real-world. Some of these inconsistencies may be more significant than others, and some knowledgebases (sets of formulae) m...